Syent is developing a low-power analog hardware layer that sits between the sensor array and a commodity microcontroller — extending what an inexpensive processor can do, without requiring new silicon on your side.
Status: pre-prototype research and development. We are seeking design partners for application-specific development.
We are rebuilding the front of the inference pipeline, replacing general-purpose compute with distributed, event-driven analog signal processing coupled directly to the sensor inputs.
Two things follow from doing this in analog organic devices. A single element — an electronic neuron — performs work that would take a large number of digital switches, so the same model needs far fewer components. And because processing and communication are driven by events rather than by a clock, the layer draws power when something happens instead of continuously.
The architecture is sensor-agnostic: signals from heterogeneous sources — acoustic, vibration, thermal, environmental — are aggregated and processed asynchronously in a single analog context. Our current prototype work is in acoustic classification; other modalities are targets for partner-led development.
Computation is distributed across many coupled analog elements rather than executed as instructions on a processor — a physical reservoir. Each element does the work of many digital switches, so component counts stay low, and tolerance to device-to-device variation is intrinsic to the approach.
Activity-driven execution eliminates idle power waste. The layer responds only to meaningful signal events, which is the basis for the sub-milliwatt power target.
Continuous sensor signals are converted into sparse, time-coded events before they reach the inference stage. Information is carried in when activity happens rather than in a stream of samples, which is what makes event-driven computation possible downstream.
The network is trained before it is deployed, against data from the sensor and environment it will actually run in. Training is a separate step from fabrication, so the same hardware can be optimised for a specific signal without a new device design. What ships to site is a fixed, characterised configuration.
Raw analog and digital streams are normalised and time-aligned across heterogeneous modalities before reaching the inference layer, which removes pre-processing overhead at the application level.
A sparse, event-driven analog architecture handles the inference front end within the power envelope of a commodity MCU, without an external accelerator and without cloud offload.
The layout is determined by the application, not fixed in advance. Channel count, filter characteristics and network topology are chosen for the signal you are actually working with, and adjusted between iterations.
The domains we are designing toward, and where we are seeking design partners. Operational intelligence without cloud infrastructure, aimed at across the domains where latency, privacy, and power constraints make centralized AI architecturally unsound.
Continuous multi-axis sensor fusion across rotating machinery, thermal arrays, and vibration inputs — inferring degradation state locally without PLC-to-cloud roundtrips.
Decentralized perceptual inference across vehicle subsystems — sensor signals fused and acted upon at the node level, preserving real-time guarantees even when network links are unavailable.
Distributed edge AI across smart building, utility, and civil infrastructure networks — anomaly detection with zero data egress and multi-year battery operation.
Always-on biosignal processing on resource-constrained wearable hardware — fusing multimodal physiological inputs with sub-milliwatt draw and fully on-device pattern recognition.
There is no single part number here, and that is deliberate. The architecture is chosen for the application, so the figures below describe the envelope we design within rather than a fixed specification.
Because fabrication is done in-house rather than at an external foundry, a revised design can be made and measured in weeks. Prototype iterations are not gated by a six-month queue.
Discuss a Design PartnershipWe work directly with engineering teams to bring Syent's analog edge layer
within existing MCU hardware. No new silicon required.
Currently seeking design partners in industrial, infrastructure and med tech applications.